This invention relates to a method of design for a CMOS output circuit (which is also called a tristate, off-chip buffer circuit) which is used in an integrated circuit (IC). In this invention when the output circuit is in its tristate mode, the external terminal connection that is inside the output circuit can tolerate a voltage level exceeding the power supply voltage of the output circuit without significant leakage current flowing through the external terminal connection.
As the transistor feature sizes of the modern Complementary Metal Oxide Semiconductors (CMOS) technology has reduced progressively by physical scaling, the supply voltages of the integrated circuits has been reduced in order to reduce the voltage stress across the gate oxide. The gate oxide voltage is a key factor in determining the long term degradation of the transistor gate oxide. Furthermore, the lower power supply voltage of an integrated circuit reduces the power dissipation which allows designers to integrate more functional blocks into a single chip. Furthermore, it has become common to combine several integrated circuits within a system using different supply voltages (for an example, supply voltages can be 1.8 volts; 2.5 volts; 3.3 volts; 5 volts) all of which share the same communication bus inside a system. To perform the proper interface between chips operated on different power supply voltages requires special circuits or devices to avoid excessive leakage current and voltage stress to the input and output circuits. The addition of special devices which can tolerant higher voltage gate stress into input and output circuits of integrated circuit can increase the reliability of said circuits, but will increase the manufacture cost as well. Where possible, it is desirable to find circuit solutions to the problems created by input and output circuits operating in a multiple-power-supply system environment.
An examination of the U.S. Pat. No. 5,151,619, J. S. Austin, R. A. Piro, and D. W. Stout disclose a CMOS off-chip driver circuit having one PMOS transistor to bias the well potential of the output pull-up PMOS transistor, another two PMOS transistors and one NMOS transistor to bias the gate of output pull-up PMOS transistor to avoid any leakage when the input voltage exceeds the power supply voltage. However, this invention does allow leakage current to flow through the output pull-up PMOS transistor when the pad voltage is driven above the positive power supply voltage of output driver immediately after the off-chip driver switches from pad voltage driven-high mode to tristate mode. There is a direct current flow through the output pull-up PMOS transistor from the pad terminal to the power supply during the period when the pad terminal voltage rises from VDD to VDD+Vthp since the gate voltage of the output pull-up PMOS transistor is around VDDxe2x88x92Vthn, and the output pull-up PMOS transistor is conducting.
In U.S. Pat. Nos. 5,160 and 5,451,889 the output driver circuit does show similar leakage when the pad voltage rises from VDD to VDD+Vth under the same conditions. In U.S. Pat. No. 5,723,992 the author disclose a low-leakage output driver circuit, which can substantially reduce the leakage through the output pull-up PMOS transistor. However, this circuit requires an additional, high power supply to bias the well potential of the output pull-up PMOS transistor.